Digital Phase Locked Loops (DPLLs) provide a low-power, small-area solution relative to analog PLLs. In a DPLL, a phase offset between a Voltage Controlled Oscillator (VCO) and a reference clock is measured by a Time-to-Digital Convertor (TDC). The measured phase is then compared with a required phase, and the result is used to correct the VCO frequency. Even though the DPLL is a phase-locked loop, knowing the frequency would be useful for many functions, such as fast PLL locking and band calibration.